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Reset (RS) Timing
Parameter
Test Conditions
Min
Max
Unit
t
dis(R)
Data bus disable time after RS
R
L = 825
-75
ns
t
d12
Delay time from RS
↓ to high-impedance SCLK
C
L = 100 pF
-
200
ns
t
d13
Delay time from RS
↓ to high-impedance DX1, DX0
-
200
ns
t
su(R)
Reset (RS) setup time prior to CLKOUT
50
-
ns
tw(R)
RS pulse duration
245
-
ns
Coprocessor Interface Timing
Parameter
Min
Nom
Max
Unit
t
d(R-A)
RD low to TBLF high
-
75
ns
t
d(W-A)
WR low to RBLE high
-
75
ns
t
a(RD)
RD low to data valid
-
80
ns
t
h(RD)
Data hold time after RD high
25
-
ns
t
su(WR)
Data setup time prior to WR high
30
-
ns
t
h(WR)
Data hold time after WR high
25
-
ns
t
w(RDL)
RD low-pulse duration
80
-
ns
t
w(WRL)
WR low-pulse duration
60
-
ns
t
wr(RBLE)
RBLE
↑ to RBLE↓
--
1
ms
M-986-2A1
www.clare.com
7
Rev. 3
CLKOUT Timing Parameters
Parameter
Test Conditions
Min
Nom
Max
Unit
t
c(C)
CLKOUT cycle time
195.27
195.31
195.35
ns
t
r(C)
CLKOUT rise time
R
L = 825
-10
-
ns
t
f(C)
CLKOUT fall time
C
L = 100 pF
-
8
-
ns
t
d(MCC)
Delay time CLKIN
↑ to CLKOUT↓
25
-
60
ns
t
d 8
Delay time CLKOUT
↓ to data bus OUT valid
-
1/4t
c(C)+75
ns
Transmitter Characteristics
Parameter
Test Conditions
Min
Typ
Max
Unit
F
OS
Frequency offset
From nominal
-
±1
Hz
TW
Twist
High/low
-
±0.5
dB
A
S
Signal amplitude
Per component
-7.40
-7.00
-6.60
dBm0
T
S
Time skew
Between components
-
0
ms
P
hi
Power due to extraneous components
-
-30
dB
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